Open Hardware: Raspberry Pi and RISC-V
Submitted by Roy Schestowitz on Sunday 12th of December 2021 02:10:43 AM
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Raspberry Pi just added an alternative version of its operating system
The Raspberry Pi company has decided to expand its Raspberry Pi OS releases from one to two branches of Debian to better support all users.
The Raspberry Pi OS legacy release will be based on Debian Buster, the 2019 release before Debian Bullseye, which was made the basis of current Raspberry Pi OS in November.
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Open Source Collaboration and Creativity Comes to Hardware [Ed: This article is mostly openwashing of a Microsoft front group, but there is a section on RISC-V]
RISC-V is a free and open source standard instruction-set architecture (ISA) for computer chips, and RISC-V International, the foundation behind it, has been around since 2015. As Calista Redmond, RISC-V’s CEO, said during a talk at the Linux Foundation Member Summit, “this is about creating commercial success, changing the game and disrupting the status quo for semiconductors.”
The growth of both RISC-V’s adoption and membership in RISC-V International’s foundation have grown exponentially recently. Membership in the foundation doubled in just the first six months of 2021, and includes chip manufacturers, software and firmware companies and the makers of connected devices. Meanwhile, nearly a quarter of hardware designs incorporate the RISC-V open ISA, including 40% of CPU designs.
Part of the increased demand for open hardware has to do with just an increased demand for hardware, period. As more and more connected devices hit the market, there are more places to incorporate open hardware. “Let’s think about that 50 billion connected IoT devices by 2030,” Redmond said. “This skyrocketing opportunity means we’re putting microprocessors in corners we never imagined.”
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Free RISC-V Training Explores Internals of Compiler Toolchains and Optimization
As RISC-V has made it easier to bring up processor chipsets, the need for compiler engineers in the RISC-V ecosystem has increased. In fact, RISC-V adoption globally has been growing at a rapid pace for several years with no end in sight, meaning this need will only grow more acute as time goes on.
That is why RISC-V International and Linux Foundation Training & Certification have partnered to release a new, free online training course on the edX platform, RISC-V Toolchain and Compiler Optimization Techniques (LFD113x). The new course, which was officially announced today at RISC-V Summit in San Francisco, is designed for engineers working with RISC-V vendors who are designing their own architectures, and those using RISC-V development boards to build applications. It is also useful for RISC-V application developers looking to improve performance or reduce the code size of their applications, toolchain developers, compiler engineers/performance engineers, and computer science students aspiring to major in systems software.
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More Chinese organizations are backing RISC-V with new CPUs • The Register
China's been scammed for billions by rogues in its chase to become a chip powerhouse, though ironically, a free, open-source CPU architecture is emerging as its best bet to create a powerful homegrown chip.
China was a winner at this week's RISC-V Summit, with many organizations introducing CPUs based on RISC-V, an open-source chip architecture sometimes called the Linux of chips. The government-backed Chinese Academy of Sciences, which is on the US Entity List, and StarFive Technology released new RISC-V chip designs for PCs and servers.
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China to upgrade mainstream RISC-V chips every six months
China is gut punching Moore's Law and the roughly one-year cadence for major chip releases adopted by the Intel, AMD, Nvidia and others.
The government-backed Chinese Academy of Sciences, which is developing open-source RISC-V performance processor, says it will release major design upgrades every six months. CAS is hoping that the accelerated release of chip designs will build up momentum and support for its open-source project.
RISC-V is based on an open-source instruction architecture, and is royalty free, meaning companies can adopt designs without paying licensing fees.
CAS' first XiangShan chip, called Yanqihu, was taped out in July 2021. Its successor, called Nanhu, was announced on Monday with major performance and architectural upgrades, and will be out early in 2022.
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Chatter around GPUs for RISC-V is growing
The activity around creating a legit graphics processor for RISC-V chip designs, an emerging competitor to x86 and ARM, is gaining steam.
Special interest groups at RISC-V next year will expand the focus on extensions for shaders and advanced matrix operations, which is important for artificial intelligence and machine learning, Mark Himelstein, chief technology officer at RISC-V, told The Register.
RISC-V International, which developed the instruction set architecture, has interest groups develop extensions that users can add to their chip designs.
In 2021, 16 RISC-V extensions were ratified, Himelstein said, and that number will grow next year. Many new extensions were part of mainstream computing chips announced this year at the RISC-V Summit.
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HiSilicon Hi3731V110 32-bit RISC-V processor is made for Full HD televisions - CNX Software
We’ve previously covered Hisilicon Hi3861V100 32-bit RISC-V microcontroller, but HiSilicon Hi3731V110 32-bit RISC-V processor designed for Full HD televisions, the company has gone up the scale with its RISC-V offerings.
The processor is equipped with an M-LVDS interface for TCON panels, CVBS output, YPbPr, VGA, and multiple HDMI 1.4 video inputs. The processor also comes with a 1080p30 VPU supporting H.265, H.264, MPEG4, MPEG2, and other codecs.
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