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Open Hardware/Modding: Raspberry Pi, RISC-V, and India

Submitted by Roy Schestowitz on Monday 6th of December 2021 06:23:38 PM Filed under
Hardware
  • Touchscreen-Powered USB Hub Selectively Powers Down Devices | Hackaday

    One of the most useful features of the Universal Serial Bus is its hot-plugging capability. You simply plug in your device, use it, and unplug it when you’re done. But what if you’ve got a huge number of USB devices? You might not want to use all of them all of the time, but repeatedly unplugging and re-plugging them is inconvenient and wears out the connectors. [Matt G] fixed this problem by building the RUNBOX: a USB hub that can be controlled through a touchscreen.

    [...]

    Although we’ve seen switchable USB hubs before, they usually require you to either press a manual switch or run dedicated software on your PC. We’ve also seen other sleek builds combining a Raspberry Pi with a USB hub.

  • open cores, ISAs, etc: what is actually open about them?

    In the past few years, with the launch of RISC-V, and IBM’s OpenPOWER initiative (backed up with hardware releases such as Talos) there has been lots of talk about open hardware projects, and vendors talking about how anyone can go and make a RISC-V or OpenPOWER CPU. While there is a modicum of truth to the assertion that an upstart company could start fabricating their own RISC-V or OpenPOWER CPUs tomorrow, the reality is a lot more complex, and it basically comes down to patents.

    [...]

    Ultimately, we come to the unavoidable topic, patents. Both RISC-V and OpenPOWER are described as patent-free, or patent-unencumbered, but what does that actually mean? In both cases, it means that the ISA itself is unencumbered by patents… in the case of RISC-V, the ISA itself is patent-free, and in the case of OpenPOWER, there is a very liberal patent licensing pool.

    But therein lies the rub: in both cases, the patent situation only covers the ISA itself. Implementation details and vendor extensions are not covered by the promises made by both communities. In other words, SiFive and IBM still have entire portfolios they can assert against any competitor in their space. RISC-V, as noted before, does not have a multilateral patent pool, and these microarchitectural patents are not covered by the OpenPOWER patent pool, as that covers the POWER ISA only.

    This means that anybody competing with SiFive or IBM respectively, would have to be a patent licensee, if they are planning to produce chips which compete with SiFive or IBM, and these licensing costs are ultimately passed through to the companies licensing the SoC cores.

    There are steps which both communities could take to improve the patent problems: for example, RISC-V could establish a patent pool, and require ecosystem participants to cross-license their patents through it, and IBM could widen the scope of the OpenPOWER patent pool to cover more than the POWER ISA itself. These steps would significantly improve the current situation, enabling truly free (as in freedom) silicon to be fabricated, through a combination of a RISC-V or OpenPOWER core and a set of supporting cores from OpenCores.

  • India reveals home-grown server that won't worry the leading edge

    Rajeev Chandrasekhar, minister of state for electronics and information technology & skill development and entrepreneurship, did reveal that some progress towards India's pursuit of its own microprocessors has also progressed. India currently developers two modestly-specced RISC-V CPUs – named Shakti and Vega – and hopes they will one day meet the nation's needs and be used around the world. With the Shakti E-Class built on a 180nm process and running at between 75Mhz and 100MHz, India is not yet a threat to incumbent market leaders. Chandrasekhar announced that a national competition to improve local CPU tech has been narrowed to ten finalists.

»

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