Devices/Hardware Leftovers


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Researchers developed fabric-friendly NFC antennas that can be woven into furniture | Arduino Blog
Near-field communication, or NFC for short, has started popping up everywhere as a way to easily pay, unlock doors, or even start a car. And now it can do one more thing: locate and track objects within a room. Researchers at Carnegie Mellon University’s Laboratory for Emerging Wireless Technologies have come up with an ingenious method to integrate NFC antennas into the fabric of pillows, furniture, and carpet to create smart environments.
Their system, which they call “TextileSense,” takes advantage of multiple-input and multiple-output (MIMO) antenna arrays to make aimed beams of radio waves that can be measured when they interact with a conductive object, like a hand.
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ESP32-C3 board comes with 16340 battery holder, Mini D1 compatibility - CNX Software
It looks like ESP32-C3 floodgates have opened. We’ve just written about several NodeMCU ESP32-C3 boards, and now there’s another board with the RISC-V WiFI & Bluetooth processor. Meet LilyGo TTGO T-OI PLUS equipped with a 16340 battery holder.
Getting a battery-powered ESP32-C3 board could prove to be very interesting as ESP32-C3 power consumption is much lower than ESP8266 and ESP32, notably in deep sleep mode, where the RISC-V processor consumes just 5uA, against 20 uA for ESP8266 and ESP32, and the difference is even greater in light sleep mode (ESP8266: 2000 uA vs ESP32-C3: 130 uA).
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Low-cost embedded router SBC offers 2.5 GbE, WiFi 6 through Qualcomm IPQ5018 SoC
Wallys Communication has been offering Qualcomm-based embedded router boards for several years, including the higher-end DR8072A with dual 2.5GbE and WiFi 6 connectivity, followed by a lower-cost WiFi 6 SBC based on IPQ6010 with Gigabit Ethernet ports.
But if you’d like to benefit from the lower cost while keeping WiFi 6 and 2.5GbE, the company has now introduced a new model based on Qualcomm IPQ5018 dual-core Cortex-A53 SoC, also found in Xiaomi Mi AX6000 router, with DR5018 embedded router board.
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Building a Curve25519 Hardware Accelerator
The “double ratchet” algorithm is integral to modern end-to-end-encrypted chat apps, such as Signal, WhatsApp, and Matrix. It gives encrypted conversations the properties of resilience, forward secrecy, and break-in recovery; basically, even if an adversary can manipulate or observe portions of an exchange, including certain secret materials, the damage is limited with each turn of the double ratchet.
The double-ratchet algorithm is a soup of cryptographic components, but one of the most computationally expensive portions is the “Diffie-Hellman (DH) key exchange”, using Elliptic Curve Diffie-Hellman (ECDH) with Curve25519. How expensive? This post from 2020 claims a speed record of 3.2 million cycles on a Cortex-M0 for just one of the core mathematical operations: fairly hefty. A benchmark of the x25519-dalek Rust crate on a 100 MHz RV32-IMAC implementation clocks in at 100ms per DH key exchange, of which several are involved in a double-ratchet. Thus, any chat client implementation on a small embedded CPU would suffer from significant UI lag.
There are a few strategies to rectify this, ranging from adding a second CPU core to off-load the crypto, to making a full-custom hardware accelerator. Adding a second RISC-V CPU core is expedient, but it wouldn’t do much to force me to understand what I was doing as far as the crypto goes; and there’s already a strong contingent of folks working on multi-core RISC-V on FPGA implementations. The last time I implemented a crypto algorithm was for RSA on a low-end STM32 back in the mid 2000’s. I really enjoyed getting into the guts of the algorithm and stretching my understanding of the underlying mathematical primitives. So, I decided to indulge my urge to tinker, and make a custom hardware accelerator for Curve25519 using Litex/Migen and Rust bindings.
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